1. Field of the Invention
This invention relates to doped wells for CMOS devices of grated circuit structures. More particularly this invention relates to a silicon substrate having an N well region and a P well region formed therein and separated by an isolation region in the substrate, and having a buried P well region formed below at least the N well region to provide enhanced latchup protection for CMOS transistors formed in the wells.
2. Description of the Related Art
As transistor areas, interconnect structures, and isolation areas continue to reduce in scale, existing designs and methods for forming CMOS transistors in side by side P wells and N wells separated by isolation regions in the substrate have become inadequate. In particular when existing CMOS structures are reduced in scale, latchup problems arise or become more acute wherein parasitic bipolar devices cause short circuits and therefore high currents flow between the power (Vdd) bus and the ground (Vss) bus, which can, in turn, cause thermal destruction of the CMOS transistors.
To avoid increasing the risk of such problems as the scale is reduced it is desirable to decrease the resistance of substrate regions outside of the conventional well regions, and the respective N well and P well resistances are maintained as low as possible. At the same time, inhibition of the flow of channel currents from one well to the other below the isolation region must be maintained, and punch through protection below the isolation regions must also be maintained.